Drain extended field effect transistors and methods of formation thereof

US9647069B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mayank Shrivastava · South Burlington, US
• Cornelius Christian Russ · Diedorf, DE
• Harald Gossner · Riemerling, DE
• Ramgopal Rao · Mumbai, IN

Key dates

• Filing date: Jun 18, 2015
• Grant date: May 9, 2017
• Expiry date: Jun 18, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/258
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.