Doped protection layer for contact formation
US9647087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Sep 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.