Low contact resistance thin film transistor
US9647133B2 · kind B2 · utility
2Cited by
3References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2014 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Nov 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned thereon and a gate insulator layer (102) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer (103) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer (104) deposited on the carrier injection layer, and (iii) a semiconductor layer (106), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.