Kuo-Hui Su
39Patents
3h-index
12Co-inventors
60Inventor score
Filing activity: Oct 10, 2003 → May 20, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10651157B1 | Semiconductor device and manufacturing method thereof | Electricity | 4 | Active |
| US8587131B1 | Through-silicon via and fabrication method thereof | Electricity | 4 | Active |
| US11444087B2 | Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same | Electricity | 3 | Active |
| US9059142B2 | Semiconductor device having vertical gates and fabrication thereof | Electricity | 2 | Active |
| US11638375B2 | Method for preparing semiconductor memory device with air gaps for reducing capacitive coupling | Electricity | 2 | Active |
| US10937790B1 | Semiconductor device with air gap structure and method for preparing the same | Electricity | 2 | Active |
| US11355342B2 | Semiconductor device with reduced critical dimensions and method of manufacturing the same | Electricity | 2 | Active |
| US9647133B2 | Low contact resistance thin film transistor | Electricity | 2 | Active |
| US10978459B2 | Semiconductor device with bit lines at different levels and method for fabricating the same | Electricity | 1 | Active |
| US8754531B2 | Through-silicon via with a non-continuous dielectric layer | Electricity | 1 | Active |
| US11309245B2 | Semiconductor device with metal spacers and method for fabricating the same | Electricity | 1 | Active |
| US7375017B2 | Method for fabricating semiconductor device having stacked-gate structure | Electricity | 1 | Active |
| US8536056B2 | Method of forming conductive pattern | Electricity | 1 | Active |
| US11521926B2 | Semiconductor device structure with serpentine conductive feature and method for forming the same | Electricity | 0 | Active |
| US8410535B2 | Capacitor and manufacturing method thereof | Electricity | 0 | Active |
| US8420477B2 | Method for fabricating a gate dielectric layer and for fabricating a gate structure | Electricity | 0 | Active |
| US11776912B2 | Method for preparing semiconductor device structure with manganese-containing lining layer | Electricity | 0 | Active |
| US12080773B2 | Recessed gate strcutre with protection layer | Electricity | 0 | Active |
| US11756885B2 | Method for fabricating semiconductor device with metal spacers | Electricity | 0 | Active |
| US11417667B2 | Method for preparing semiconductor device with air gap structure | Electricity | 0 | Active |
| US12009212B2 | Semiconductor device with reduced critical dimensions | Electricity | 0 | Active |
| US10840136B1 | Method for preparing conductive via | Electricity | 0 | Active |
| US12256565B2 | Method for preparing recessed gate structure with protection layer | Electricity | 0 | Active |
| US12218053B2 | Semiconductor device with metal spacers and method for fabricating the same | Electricity | 0 | Active |
| US8003528B2 | Semiconductor structure and method for making the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.