Stress reduction interposer for ceramic no-lead surface mount electronic device
US9648729B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2015 |
| Grant date | May 9, 2017 |
| Priority date | — |
| Expiry date | Nov 20, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.