Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines
US9652230B2 · kind B2 · utility
1Cited by
6References
20Claims
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Key dates
| Filing date | Oct 15, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 1, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.