Instruction and logic for non-blocking register reclamation
US9652236B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Dec 23, 2013 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Aug 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.