Banked physical register data flow architecture in out-of-order processors
US9652246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jun 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of executing instructions in a processing system, respective global age tags are assigned to each of the one or more instructions fetched for processing by the processing system. Each global age tag indicates an age of the corresponding instruction in the processing system. Respective physical registers in a physical register file are allocated to each destination logical register referenced by each instruction. The respective global age tags are written to the in respective physical registers allocated to the destination logical registers of the instructions. The instructions are executed by the processing system. At least some of the instructions are executed in an order different from a program order of the instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.