GPU divergence barrier
US9652284B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2013 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jan 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory, and at least one programmable processor configured to determine, for each warp of a plurality of warps, whether a Boolean expression is true for a corresponding thread of each warp, pause execution of each warp having a corresponding thread for which the expression is true, determine a number of active threads for each of the plurality of warps for which the expression is true, sort the plurality of warps for which the expression is true based on the number of active threads in each of the plurality of warps, swap thread data of an active thread of a first warp of the plurality of warps with thread data of an inactive thread of a second warp of the plurality of warps, and resume execution of the at least one of the plurality of warps for which the expression is true.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.