Method and apparatus for performing logic synthesis
US9652572B2 · kind B2 · utility
0Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2013 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Feb 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.