Simultaneous multi-layer fill generation
US9652574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2011 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design un…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.