Integrated circuit layout design system and method
US9652580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2015 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | May 14, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.