In-memory computational device
US9653166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2016 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Jul 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device includes a memory array built of several sections having memory cells arranged in rows and column, at least one cell in each column of the memory array being connected to a bit line; and at least one multiplexer to connect a bit line in a first column of a first section to a bit line in a second column in a second section different from the first section, where the second column is not continuous with the first column ; and a decoder to activate at least two word lines of the first section and a word line connected to a cell in the second column in the second section to write a bit line voltage associated with a result of a logical operation performed on the first column into the cell in the second column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.