Semiconductor integrated circuit with nano gap
US9653349B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jan 24, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.