Electrostatic discharge (ESD) diode in FinFET technology
US9653448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | May 16, 2017 |
| Priority date | — |
| Expiry date | Nov 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.