Patent · US Active

Updating of shadow registers in N:1 clock domain

US9658852B2 · kind B2 · utility

0Cited by

5References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Thomas Koehler · Holzgerlingen, DE
Frank Lehnert · Weil im Schönbuch, DE

Key dates

Filing date	Jul 15, 2015
Grant date	May 23, 2017
Priority date	—
Expiry date	Jul 15, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/30138
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.