Inventor · Holzgerlingen, DE

Thomas Koehler

23Patents
3h-index
28Co-inventors
63Inventor score

Filing activity: Aug 10, 1995 → Mar 15, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US5996063A Management of both renamed and architected registers in a superscalar computer system Physics 15 Expired
US10380033B2 Multi-engine address translation facility Physics 5 Active
US8135960B2 Multiprocessor electronic circuit including a plurality of processors and electronic data processing system Physics 3 Active
US8166249B2 Performing a least recently used (LRU) algorithm for a co-processor Physics 2 Active
US10025608B2 Quiesce handling in multithreaded environments Physics 2 Active
US10083124B1 Translating virtual memory addresses to physical addresses Physics 1 Active
US9715458B2 Multiprocessor computer system Physics 1 Active
US8594321B2 Apparatus and method for operating a symmetric cipher engine in cipher-block chaining mode Electricity 1 Active
US10380032B2 Multi-engine address translation facility Physics 1 Active
US5694400A Checking data integrity in buffered data transmission Physics 1 Expired
US10929312B2 Zone-SDID mapping scheme for TLB purges Emerging Cross-Sectional Technologies 0 Active
US8966221B2 Translating translation requests having associated priorities Physics 0 Active
US10353827B2 Zone-SDID mapping scheme for TLB purges Emerging Cross-Sectional Technologies 0 Active
US10176002B2 Quiesce handling in multithreaded environments Physics 0 Active
US10956341B2 Multi-engine address translation facility Physics 0 Active
US11775444B1 Fetch request arbiter Physics 0 Active
US8250336B2 Method, system and computer program product for storing external device result data Physics 0 Active
US10635603B2 Multi-engine address translation facility Physics 0 Active
US10621105B2 Multi-engine address translation facility Physics 0 Active
US10127159B1 Link consistency in a hierarchical TLB with concurrent table walks Emerging Cross-Sectional Technologies 0 Active
US10353828B2 Zone-SDID mapping scheme for TLB purges Emerging Cross-Sectional Technologies 0 Active
US10140217B1 Link consistency in a hierarchical TLB with concurrent table walks Emerging Cross-Sectional Technologies 0 Active
US9658852B2 Updating of shadow registers in N:1 clock domain Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.