Implementing hardware accelerator for storage write cache management
US9658968B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Nov 12, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Dec 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.