Modeling pattern dependent effects for a 3-D virtual semiconductor fabrication environment
US9659126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improving semiconductor device fabrication by enabling the identification and modeling of pattern dependent effects of fabrication processes is discussed. In one embodiment a local mask is generated from a 3-D model of a semiconductor device structure that was created in a 3-D virtual semiconductor fabrication environment from 2-D design layout data and a fabrication process sequence. The local mask is combined with a global mask based on the original design layout data to create a combined mask. The combined mask is convolved with at least one proximity function to generate a loading map which may be used to modify the behavior of one or more processes in the process sequence. This behavior modification enables the 3-D virtual semiconductor fabrication environment to deliver more accurate 3-D models that better predict the 3-D device structure when performing the virtual semiconductor device fabrication that serves as a prelude to physical fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.