Memory having a plurality of resistive non-volatile memory cells
US9659623B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive non-volatile memory (NVMN) cell has three select transistors connected together in series. A first resistive element has a first terminal connected between first and second select transistors and a second terminal. A second resistive element has a first terminal connected between second and third transistors. In a first embodiment, the second terminals of the first and second resistive elements are connected to bit lines. In a second embodiment, the second terminals of the first and second resistive elements are connected to source lines. In the first embodiment, when the center select transistor is conductive, the first and second resistive elements become a resistor-divider. Each of the first and second resistive elements include a magnetic tunnel junction (MTJ).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.