Semiconductor memory apparatus and data scrambling method using the same
US9659659B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jan 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus and a data processing method are provided. The semiconductor memory apparatus gives consideration to partial page programming and data scrambling, and improves the reliability. In the flash memory of the present invention, when data is programmed to a page n times consecutively, identification information and program information are generated. A scrambled data, the location information and the flag information are programmed to a selected page in a memory array. The location information indicates a storage location for a data scrambling in the page selected based on an input address information. The flag information is used to identify a storage region specified by the location information is programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.