Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile

US9659825B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Deborah J. Riley · Sachse, US
• Seung-Chul Song · Plano, US

Key dates

• Filing date: Jun 22, 2015
• Grant date: May 23, 2017
• Expiry date: Jun 22, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.