Embedded packaging for devices and systems comprising lateral GaN power transistors

US9659854B2 · kind B2 · utility

Assignee

• GaN Systems Inc. · CA

Inventors

• Greg P. Klowak · Ottawa, CA
• Ahmad Mizan · Gatineau, CA
• John Roberts · Ottawa, CA

Key dates

• Filing date: Apr 15, 2015
• Grant date: May 23, 2017
• Expiry date: Apr 15, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/471
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.