Method and structure to contact tight pitch conductive layers with guided vias
US9659860B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2013 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Aug 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.