Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
US9659864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.