Three-dimensional memory structures with low source line resistance
US9659866B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Dielectric pedestal structures embedded in a sacrificial material layer is formed between a substrate and an alternating stack of insulating layers and spacer material layers. After memory openings are formed through the alternating layer, a cavity is formed by removal of the sacrificial material layer selective to the dielectric pedestal structures. A memory film, a semiconductor channel layer, and a dielectric core are sequentially formed in the volume including the cavity and the memory openings. A backside trench is formed through the alternating stack in an area that straddles the dielectric pedestal structures. By recessing the dielectric pedestal structures selective to the semiconductor channel layer, planar regions and vertical regions of the semiconductor channel layer can be physically exposed, which are converted into source regions. Contact resistance can be lowered due the increased contact area provided by vertical source portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.