Semiconductor devices
US9659959B2 · kind B2 · utility
10Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Oct 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.