Flash memory and method of manufacturing the same
US9660106B2 · kind B2 · utility
0Cited by
24References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2014 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Aug 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.