Integration of spintronic devices with memory device
US9660183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.