Distributed driver circuitry integrated with GaN power transistors
US9660639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.