Delay compensation
US9660656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | May 23, 2017 |
| Priority date | — |
| Expiry date | May 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.