Power control over memory cell arrays
US9666266B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | May 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.