Three-dimensional one-time-programmable memory comprising off-die address/data-translator
US9666300B2 · kind B2 · utility
12Cited by
49References
20Claims
0Family size
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Key dates
| Filing date | Oct 24, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a three-dimensional one-time-programmable memory (3D-OTP) comprising an off-die address/data-translator (A/D-translator). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least an A/D-translator of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The A/D-translator converts at least an address and/or data between logic and physical spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.