Integrated circuit having thinner gate dielectric and method of making
US9666483B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2012 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | May 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.