3D stacked-chip package
US9666520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Aug 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.