Three-dimensional semiconductor memory device
US9666525B2 · kind B2 · utility
10Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Jul 5, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jul 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.