Package substrate differential impedance optimization for 25 GBPS and beyond
US9666544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace. At 8 ps rise time, a <5% impedance variation is obtained with a 0.8 mm BGA ball pitch and a 10-layer buildup substrate and a <10% impedance variation is obtained with a 1 mm BGA ball pitch and a 14-layer buildup substrate. The method is applicable to all BGA package designs running at 25 Gb/s and beyond.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.