Multi-layer metal pads
US9666546B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Apr 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.