Epitaxy profile engineering for FinFETs
US9666691B2 · kind B2 · utility
6Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | May 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02636
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.