Non-planar semiconductor structure with preserved isolation region
US9666709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.