Package carrier and manufacturing method thereof
US9668351B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 15, 2015 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Aug 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the connecting surface of the carrier and completely covers the connecting surface. A substrate having an upper surface and a lower surface opposite to each other is provided. A first patterned solder resist layer is formed on the lower surfaces of the substrate and exposes a portion of the lower surface. The carrier and the substrate are laminated, the releasable solder resist layer directly contacts the first patterned solder resist layer, and the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder resist layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.