Lithographic plane check for mask processing
US9671685B2 · kind B2 · utility
4Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jul 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/86
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.