Low power operation for flash memory system
US9672930B2 · kind B2 · utility
3Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2015 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | May 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.