Patent · US Active

Process for fabricating an integrated circuit comprising at least one coplanar waveguide

US9673088B2 · kind B2 · utility

0Cited by

4References

17Claims

0Family size

Assignee

STMicroelectronics SA

Inventors

Sylvain Joblot · Grenoble, FR
Pierre Bar · Grenoble, FR

Key dates

Filing date	Dec 16, 2015
Grant date	Jun 6, 2017
Priority date	—
Expiry date	Dec 16, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01P11/003
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.