Vertical thin film transistors with surround gates
US9673257B1 · kind B1 · utility
182Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jun 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.