Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
US9673304B1 · kind B1 · utility
7Cited by
0References
20Claims
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Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Jun 6, 2017 |
| Priority date | — |
| Expiry date | Jul 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.