Integrated circuit structures with spin torque transfer magnetic random access memory and methods for fabricating the same

US9673388B2 · kind B2 · utility

Assignee

• GlobalFoundries Singapore Pte. Ltd. · SG

Inventors

• Eng Huat Toh · Singapore, SG
• Xuan Anh Tran · Singapore, SG
• Elgin Quek · Singapore, SG

Key dates

• Filing date: Oct 20, 2014
• Grant date: Jun 6, 2017
• Expiry date: Nov 30, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/10

Abstract

A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.