Inventor · Singapore, SG

Elgin Quek

152Patents

21h-index

85Co-inventors

93Inventor score

Filing activity: Feb 27, 1995 → Aug 17, 2020

Most-cited inventions

Patent	Title	Area	Cited by	Status
US6300177A	Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials	Electricity	160	Expired
US7169675B2	Material architecture for the fabrication of low temperature transistor	Electricity	149	Expired
US7867835B2	Integrated circuit system for suppressing short channel effects	Electricity	115	Active
US6461900B1	Method to form a self-aligned CMOS inverter using vertical device integration	Electricity	92	Expired
US6946349B1	Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses	Emerging Cross-Sectional Technologies	80	Expired
US6747314B2	Method to form a self-aligned CMOS inverter using vertical device integration	Electricity	72	Expired
US7592270B2	Modulation of stress in stress film through ion implantation and its application in stress memorization technique	Electricity	53	Active
US6632712B1	Method of fabricating variable length vertical transistors	Electricity	49	Expired
US6313008A	Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon	Electricity	45	Expired
US6403485B1	Method to form a low parasitic capacitance pseudo-SOI CMOS device	Electricity	38	Expired
US8440533B2	Self-aligned contact for replacement metal gate and silicide last processes	Electricity	31	Active
US5488244A	Electrically erasable and programmable read only memory cell	Electricity	30	Expired
US6406945B1	Method for forming a transistor gate dielectric with high-K and low-K regions	Emerging Cross-Sectional Technologies	30	Expired
US6417056B1	Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge	Electricity	30	Expired
US6306715A	Method to form smaller channel with CMOS device by isotropic etching of the gate materials	Electricity	27	Expired
US6468877B1	Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner	Electricity	25	Expired
US6468851B1	Method of fabricating CMOS device with dual gate electrode	Electricity	24	Expired
US6436770B1	Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation	Electricity	22	Expired
US8492235B2	FinFET with stressors	Electricity	22	Active
US6511884B1	Method to form and/or isolate vertical transistors	Electricity	22	Expired
US8502279B2	Nano-electro-mechanical system (NEMS) structures with actuatable semiconductor fin on bulk substrates	Electricity	21	Active
US8368127B2	Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current	Electricity	18	Active
US9673388B2	Integrated circuit structures with spin torque transfer magnetic random access memory and methods for fabricating the same	Electricity	15	Active
US6277710A	Method of forming shallow trench isolation	Electricity	14	Expired
US8889494B2	Finfet	Electricity	13	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.