Two-step interconnect testing of semiconductor dies
US9678142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2014 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.