Electrical interconnect for an integrated circuit package and method of making same
US9679837B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | Jun 13, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical interconnect assembly includes an insulating substrate, upper conductive pads coupled to a top surface of the insulating substrate, and lower conductive pads coupled to a bottom surface of the insulating substrate. The upper conductive pads and the lower conductive pads comprise an electrically conductive material. A metallization layer is deposited on the top surface of the insulating substrate and the upper conductive pads. The metallization layer extends through vias formed through a thickness of the insulating substrate to contact a top surface of the lower conductive pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.